Unlanded vias with a low dielectric constant material as an intraline dielectric
US6365971B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 1999 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | May 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an unlanded via over a polymer that is used as an intraline or intralayer dielectric is described. In one embodiment, the present invention creates an etch-stop layer for forming unlanded vias using three steps. A recess is created in an intraline dielectric, such as an organic polymer. An etch-stop layer is then deposited over the intraline dielectric. The etch-stop layer is then polished back before depositing a final insulating layer. The unlanded via is formed by etching through the final insulating layer. The intraline dielectric is protected by the etch-stop layer during the etch of the final insulating layer to form the unlanded via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.