Method and apparatus for buffering an input-output node of an integrated circuit
US6366129B1 · kind B1 · utility
18Cited by
11References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1998 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Nov 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input-output (I-O) buffer for an integrated circuit. The buffer includes a controller and first and second groups of transistors to pull the node up and down, respectively. The controller is configured to turn on a transistor from the first group to drive a high bit on the node during a first period of time. The controller is further configured to turn on transistors from both the first and second groups, simultaneously, to terminate the node during a second period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.