High speed readout architecture for analog storage arrays
US6366320B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1997 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Dec 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/76
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit having an analog storage array, a sense amplifier array in which each sense amp cell generates a differential signal pair in response to receiving first and second signals from the storage array. The circuit also includes an analog multiplexer through which a selected differential signal pair is driven into a signal processing pipe. In another embodiment, the sense amp cells each include an operational amplifier (opamp) pair configured as unity-gain closed loop amplifiers for driving the differential signal pair through the analog multiplexer. To improve settling time, the opamps are designed to provide an underdamped response while loaded with the analog transmission path through the analog mux. In yet another embodiment, each sense amp cell is activated one clock cycle before it is read. This allows speedy readout while transitioning from one cell to the next. Also, maintaining only two cells active at any given time during readout helps reduce power dissipation and substantially decouples power dissipation in the sense amp array from the size of the array. The embodiments of the invention can be used in different types of imaging systems, including for in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.