CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY-SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY-TOLERANT EXTERIOR PADS THROUGH MULTIPLE REDUNDANT VIAS
US6366443B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Dec 9, 1997 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Dec 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/162
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A ceramic capacitor typically 10 mils to 340 mils square by typically 4-20 mils thickness with areas of metallization, or pads, to which electrical connections may be made on, typically, each of two opposite exterior surfaces, has embedded at least one, and normally two or more, metallization planes at close, typically 0.5 mil, separation. Each interior metallization plane connects through multiple redundant vias, as are preferably made by (ii) punching, (ii) drilling, (iii) laser drilling, or (iv) radiation patterning of a green ceramic sheet having a photosensitive binder, to an associated surface pad or trace. The vias are both numerous and redundant, typically being of 2 mil diameter on 10 mil centers in a pin grid array pattern over and through entire ceramic layers of the capacitor, permitting both (i) easy fabrication without exacting alignment or registration between layers, and (ii) low Equivalent Series Resistance (ESR) in the finished capacitor. The composite structure so created exhibits increased capacitance over that which would alternatively exist should no electrically-connected interior metallization planes be present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.