Ferroelectric non-volatile memory cell integrated in a semiconductor substrate
US6366488B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Presented is a ferroelectric non-volatile memory cell in a semiconductor substrate that has a MOS device connected in parallel to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower electrode formed on the insulating layer above the first conduction terminals and are electrically coupled to them. The lower electrode of the ferroelectric capacitor is covered with a layer of ferroelectric material and coupled capacitively to an upper electrode. The upper electrode is formed above the second conduction terminals and are electrically connected thereto, and extends over the ferroelectric material to at least partially overlap the lower electrode. Also presented is a non-volatile memory matrix that includes a plurality of the ferroelectric memory cells that are organized into rows and columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.