Reduction of noise in memory integrated circuits with dedicate power supply bus and ground bus for sense amplifiers
US6366513B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 12, 2000 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Jan 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory integrated circuit (100) includes a core cell array (102) having a plurality of core cells for storing data in one of a plurality of states, a plurality of power supply buses (140, 142, 144, 146) including a sensing power supply bus (144) and a sensing ground bus (146) dedicated to sensing states of core cells. The integrated circuit firther includes a sense threshold generating circuit (126) which generates a sense threshold signal in response to a power supply potential on the sensing power supply bus and a ground potential of the sensing ground bus. The integrated circuit still further includes a plurality of sense amplifiers (108) which detect the states of core cells in relation to the sense threshold signal. The sense amplifiers are coupled to the sensing power supply bus and the sensing ground bus so that substantially all power supply noise at the plurality of sense amplifiers and the sense threshold generator is common node noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.