Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO
US6366979B1 · kind B1 · utility
3Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1997 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit that allows for short retransmit recovery times by implementing a read cache memory in a FIFO device. A circuit comprising a memory array, a cache memory and a logic circuit. The memory array includes a read pointer, a write pointer and a plurality of memory rows. The cache memory is configured to store one or more memory data bits. The logic circuit is further configured to control the output of the circuit by presenting either (i) an output from the memory array or (ii) an output from the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.