Daniel Eric Cress
10Patents
4h-index
8Co-inventors
42Inventor score
Filing activity: Dec 18, 1996 → Sep 29, 2000
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6473357B1 | Bitline/dataline short scheme to improve fall-through timing in a multi-port memory | Physics | 17 | Expired |
| US6483386B1 | Low voltage differential amplifier with high voltage protection | Electricity | 16 | Expired |
| US6191636A | Input buffer/level shifter | Electricity | 8 | Expired |
| US6442657B1 | Flag generation scheme for FIFOs | Physics | 4 | Expired |
| US6526470B1 | Fifo bus-sizing, bus-matching datapath architecture | Physics | 4 | Expired |
| US5860160A | High speed FIFO mark and retransmit scheme using latches and precharge | Physics | 4 | Expired |
| US6366979B1 | Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO | Physics | 3 | Expired |
| US6023435A | Staggered bitline precharge scheme | Physics | 2 | Expired |
| US6292013A | Column redundancy scheme for bus-matching fifos | Physics | 1 | Expired |
| US6055177A | Memory cell | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.