System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch
US6367005B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Oct 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4484
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method in a processor to perform a backing store switch from a first context (source context) to a second context (target context) is provided whereby the backing store memory image and RSE will be synchronized with the processor's execution of instructions. The processor includes a register stack (RS) device that includes a portion allocated for dirty registers. The portion is defined by first and second physical register numbers. The processor further includes a register stack engine (RSE) to exchange information in one of an instruction execution dependent and independent modes between a storage area and the RS. The processor further includes a FLUSHRS state machine to notify the RSE to store dirty register in the RS to a backing store located in a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.