Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation
US6367065B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Apr 2, 2002 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design tool to support design of a N-NARY logic circuit is described. The designer develops a syntax statement that comprises encoded information according to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the N-NARY logic circuit and the specific configuration of transistors required to build the N-NARY logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the N-NARY circuit and a physical circuit description of the N-NARY circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.