Method of manufacturing a semiconductor device
US6368915B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Mar 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
In a method of manufacturing a semiconductor device comprising a non-volatile memory element, an active region 4 of a first conductivity type is defined at a surface 2 of a semiconductor body 1, and a patterned layer is applied, which patterned layer acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. Then, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer 14. In this recess a first insulating layer is applied providing a floating gate dielectric 19, to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer 14, which first conductive layer is shaped into a floating gate 21 by means of masked etching. The floating gate 21 has a substantially flat surface portion 22 extending substantially parallel to the surface 2 of the semiconductor body 1 and sidewall portions 23 exte…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.