Delta sigma D/A converter
US6369731B1 · kind B1 · utility
6Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Nov 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3042
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The problem of the present invention is, in a plural-number order delta sigma D/A converter, not to cause click noise upon performing mute operation at no-signal input idling and hence to eliminate the necessity of a circuit for removing this.In order to perform sequence operation for rendering zero an output signal by lowering the order of a loop filter in order when stopping the operation of a plural-number order delta sigma D/A converter, 1st-order differentiators corresponding to each order and switch means for rendering inputs to these 1st-order differentiators zero are provided in the loop filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.