Patent · US Expired

Method for testing a multiplicity of word lines of a semiconductor memory configuration

US6370069B2 · kind B2 · utility

7Cited by

7References

6Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Eckhard Brass · Unterhaching, DE
Thilo Schaffroth · Weingarten, DE
Joachim Schnabel · Hersbruck, DE
Helmut Schneider · Hersbruck, DE

Key dates

Filing date	May 29, 2001
Grant date	Apr 9, 2002
Priority date	—
Expiry date	May 29, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/26
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.