Way to compensate the effect of coupling between bitlines in a multi-port memories
US6370078B1 · kind B1 · utility
15Cited by
2References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Dec 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a system and method of compensating for coupling capacitance between bit lines in multi-port memories. The complementary bit lines are switched between a core cell and a modified core cell. The modified core cell may invert the connections to the access transistors. This results in the writing of data into the cell correctly while compensating for coupling capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.