Method and apparatus for lock synchronization in a microprocessor system
US6370625B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Dec 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.