Michael D. Upton
23Patents
11h-index
30Co-inventors
75Inventor score
Filing activity: Jan 21, 1992 → Mar 14, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5351197A | Method and apparatus for designing the layout of a subcircuit in an integrated circuit | Electricity | 145 | Expired |
| US6370625B1 | Method and apparatus for lock synchronization in a microprocessor system | Physics | 82 | Expired |
| US6018786A | Trace based instruction caching | Physics | 77 | Expired |
| US6170038A | Trace based instruction caching | Physics | 41 | Expired |
| US6216234A | Processor having execution core sections operating at different clock rates | Physics | 36 | Expired |
| US6138225A | Address translation system having first and second translation look aside buffers | Emerging Cross-Sectional Technologies | 35 | Expired |
| US6094717A | Computer processor with a replay system having a plurality of checkers | Physics | 27 | Expired |
| US6735688B1 | Processor having replay architecture with fast and slow replay paths | Physics | 26 | Expired |
| US6651158B2 | Determination of approaching instruction starvation of threads based on a plurality of conditions | Physics | 25 | Expired |
| US5828868A | Processor having execution core sections operating at different clock rates | Physics | 24 | Expired |
| US6643747B2 | Processing requests to efficiently access a limited bandwidth storage area | Physics | 18 | Expired |
| US6487675B2 | Processor having execution core sections operating at different clock rates | Physics | 10 | Expired |
| US6256745A | Processor having execution core sections operating at different clock rates | Physics | 7 | Expired |
| US7454600B2 | Method and apparatus for assigning thread priority in a processor or the like | Physics | 7 | Expired |
| US7010669B2 | Determining whether thread fetch operation will be blocked due to processing of another thread | Physics | 7 | Expired |
| US9465670B2 | Generational thread scheduler using reservations for fair scheduling | Physics | 6 | Active |
| USRE44494E1 | Processor having execution core sections operating at different clock rates | General | 4 | Expired |
| US7085889B2 | Use of a context identifier in a cache memory | Physics | 2 | Expired |
| US7987346B2 | Method and apparatus for assigning thread priority in a processor or the like | Physics | 1 | Active |
| US9785436B2 | Apparatus and method for efficient gather and scatter operations | Physics | 1 | Active |
| USRE45487E1 | Processor having execution core sections operating at different clock rates | General | 0 | Active |
| US8850165B2 | Method and apparatus for assigning thread priority in a processor or the like | Physics | 0 | Active |
| US7877583B2 | Method and apparatus for assigning thread priority in a processor or the like | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.