Apparatus for testing memory in a microprocessor
US6370661B1 · kind B1 · utility
31Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1999 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Apr 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.