Data hierarchy layout correction and verification method and apparatus
US6370679B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1998 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Sep 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.