Self-aligned trench capacitor capping process for high density DRAM cells

US6372573B1 · kind B1 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Masami Aoki · Hiratsuka, JP
• Hirofumi Inoue · Kamakura, JP
• Bruce W. Porth · Jericho, US
• Max G. Levy · South Burlington, US
• Victor R. Nastasi · Hopewell Junction, US
• Emily E. Fisch · Burlington, US
• Paul C. Buschner · Colchester, US

Key dates

• Filing date: Oct 26, 1999
• Grant date: Apr 16, 2002
• Expiry date: Oct 26, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0385

Abstract

A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.