Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing
US6372605B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jun 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In one implementation wet-etching and/or sputter etch-back (SEB) is performed prior to applying a reverse-tone mask. In another implementation a wet etching step is performed after the reverse-tone mask is stripped. One significant result of each of these steps is a reduction in the height and width of at least some of the oxide horns that remain after the reverse-tone mask is stripped. As such, the oxide structures that need to be planarized during CMP will be smaller than those of the prior art. Moreover, since the resulting oxide structures that need to be planarized by CMP processing are smaller, the oxide layer can be initially applied at a smaller thickness than that of the prior art. As such, the duration of CMP processing can be correspondingly shorter, resulting in polished semiconductor wafer surfaces with greater uniformity than that provided by the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.