Method for forming multi-level metal interconnection
US6372649B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Aug 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.