NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area

US6373095B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John A. Bracchitta · South Burlington, US
• James S. Nakos · Saint Johnsbury Center, US

Key dates

• Filing date: Feb 25, 1998
• Grant date: Apr 16, 2002
• Expiry date: Feb 25, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6891

Abstract

A field effect floating gate transistor forming an NVRAM cell is disclosed. A substrate having field isolation structures includes therebetween a doped region forming a channel connecting a source and drain. An oxide layer is disposed over said channel forming a tunneling oxide layer for the device. A layer of polysilicon extends over the oxide layer, to each of the isolation structures and then extends upwards forming a U-shaped pillar floating gate. A second oxide layer disposed within the interior of the U-shaped floating gate supports a control gate. A second layer of polysilicon formed over the second oxide layer forms a control gate, and is connected to a conductor which is common to a row of such cells within a memory. The control gate is coupled to the floating gate through the second oxide layer to the upwardly extending layer of the floating gate as well as over the portion of the floating gate extending over the channel.