Ferroelectric memory and method of operating same
US6373743B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric non-volatile memory comprising: a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs having a source, a drain, a substrate, and a gate. The FETs are arranged in an array comprising a plurality of rows and a plurality of columns. There are a plurality of row select lines, each associated with one of the rows of said ferroelectric FETs, and a plurality of column select lines, each associated with one of the columns of ferroelectric FETs. Each of the sources is directly electrically connected to its associated row select line, and each of the drains is directly electrically connected to its associated column select line. The source and substrate of each FET are also directly electrically connected. A memory cell is read by connecting its row select line to ground, and its column select line to a small voltage. All the gates, and the row select lines of non-selected cells are open or connected to a high resistance source. Thus, the current in the selected column select line and row select line is a measure of the state of the selected cell. Each FET is fabricated using a self-aligned process so that no portion of a source/drai…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.