Dynamic ram and semiconductor device
US6373776B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 14, 2001 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Mar 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided a plurality of memory mats, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells coupled to the plurality of bit lines, and the plurality of word lines are provided in a direction of the bit line. A sense amplifier array including a plurality of latch circuits is provided in areas between the memory mats arranged in the bit line direction, respectively, and a pair of input/output nodes of which are connected to a pair of bit lines separately placed in the memory mats on both sides of the area, respectively. In this case, for a general memory mat other than both end portions in the bit line direction, word lines in any one of the memory mats are activated, while, for end memory mats provided on both end portions in the bit line direction, word lines of both memory mats are activated together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.