Process for manufacturing buried channels and cavities in semiconductor material wafers
US6376291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Apr 25, 2020 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0177
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.