Method of making gate wiring layer over semiconductor substrate
US6376347B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Sep 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of making a gate wiring layer, in which a carbon-based layer is patterned by dry etching using a gas that does not etch a gate insulating layer so as to form a gate wiring layer without deteriorating the gate insulating layer and without etching the semiconductor substrate. In forming a gate insulating layer and a gate wiring layer on a semiconductor substrate, a carbon-based layer is formed on a semiconductor substrate, followed by forming a predetermined mask on the layer for patterning the layer. The carbon-based layer is etched by dry etching using an oxygen gas, a carbon monoxide gas or a mixed gas containing an oxygen gas, a nitrogen gas, a carbon monoxide gas and an argon gas and without containing a halogen gas. The etching is selectively stopped by the insulating layer. The insulating layer of, for example, SiO2 is etched by dry etching using a halogen-containing gas, but is scarcely etched by dry etching using an oxygen-containing gas that does not contain a halogen gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.