Forming method of copper interconnection and semiconductor wafer with copper interconnection formed thereon
US6376363B1 · kind B1 · utility
13Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Aug 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a wafer edge neighboring region 26, the circumference end part of a silicon oxide film 8 is set in an outer position than the circumference end part of a silicon oxide film 3 and thereby a structure in which polishing remains 21 generated in forming a copper interconnection comprising a copper film 6 and the like are covered with the silicon oxide film 8 is attained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.