Vertical DRAM cell with robust gate-to-storage node isolation
US6376873B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Apr 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/053
Abstract
A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.