Circuit and method for PMOS device N-well bias control
US6377112B1 · kind B1 · utility
175Cited by
6References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Dec 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
Abstract
An N-Well bias control circuit (18) is provided which receives a first voltage (VS) and second voltage (VD) of different magnitudes relating to a battery voltage (Vbatt) and an output voltage (Vout) of an up/down DC-DC converter. The bias control circuit provides the voltage of largest magnitude to an output node (VN-Well), which is used to properly bias the N-Well region of a PMOS transistor (26) to minimize the probability of latch up. The N-Well bias control circuit may also be modified to deliver the minimum of two voltages, Vbatt or Vout, to properly bias the P-Well region of an NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.