Block architecture option circuit for nonvolatile semiconductor memory devices
US6377486B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jun 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device is described, which comprises a memory cell array, a block address input circuit, and a block selection circuit. The memory cell array includes a plurality of normal blocks for storing normal data, and a plurality of boot blocks for storing boot codes initializing a system. Further, the nonvolatile semiconductor memory device has a plurality of boot block architecture options. The boot block input circuit receives an external block address, and coverts the external block address into an internal block address in accordance with selected one of a plurality of the boot block architecture options. Further, the block address input circuit includes an option selection feature having a pair of terminals. The block selection circuit selects corresponding one of the blocks of the memory cell array in response to the internal block address. The selecting one of the boot block architecture options is determined by electric connection/disconnection of the terminals of the option selection feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.