Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry
US6377970B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.