Interrupt descriptor cache for a microprocessor
US6378023B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jan 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt descriptor cache for a microprocessor is provided which is configured to store interrupt information associated with a plurality of interrupt vectors. Prior to fetching interrupt information from a main memory of a computer system, the microprocessor searches the interrupt descriptor cache. If the interrupt information is stored therein, the address of the interrupt service routine is formed from the stored interrupt information instead of fetching the interrupt information from main memory. The interrupt descriptor cache is additionally configured to monitory memory accesses for updates to the interrupt information stored therein. If a memory location storing interrupt information is updated, then the interrupt descriptor cache invalidates any storage locations which may be storing the information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.