Semiconductor integrated circuit supervising an illicit address operation
US6378078B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Mar 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A supervisory circuit for a semiconductor integrated circuit includes a first circuit, a second circuit, inverters, and an EXOR circuit. The first circuit outputs an address signal. The second circuit receives via an address bus the address signal transferred from the first circuit. The inverters hold at least an address signal preceding one transfer period as a past address signal on the address bus. The EXOR circuit compares the past address signal held by the inverters with a current address signal on the address bus, and when the comparison result represents that the past and current address signals are identical, outputs an illicit operation detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.