Parity checking circuit
US6378108B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for checking the parity of the contents of a register is provided. The register has a test mode in which a scan input of each flip-flop in the register is connected to a scan output of a preceding flip-flop to form a scan path. The parity checking circuit includes an XOR gate for at least each flip-flop from the second flip-flop to the last flip-flop of the register. Each XOR gate has one input connected to the normal output of the associated flip-flop, another input connected to the scan input for the flip-flop, and an output connected to the scan output of the flip-flop when not in the test mode. The result of the parity checking operation is generated at the output of the XOR gate associated with the last flip-flop of the register. In preferred embodiments, for each flip-flop of the register, the normal output of the flip-flop is supplied to the scan output in the test mode, and the output of the associated XOR gate is supplied to the scan output when not in the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.