Layer-based rule checking for an integrated circuit layout
US6378110B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method for verifying a physical layout of an integrated circuit design for a semiconductor chip. The physical layout is specified in terms of a plurality of layers used to fabricate the chip. Initially, a pre-defined set of rules are stored in memory. These rules are used to specify certain dimensions for properly laying out the physical design of the IC. For each rule, one or more layers applicable to that rule is specified. Instead of reading a rule and then applying that rule to the relevant portions of the physical layout, the present invention reads one or more layers pertaining to the physical layout and then determines all rules applicable to those layers. The layers are then verified against the appropriate rules. Any error conditions are stored for subsequent display to the designer or engineer. By performing a layer based rule checking scheme, the number of read operations required, which reduces the time it takes to perform the verification process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.