Method of fabricating a micromechanical semiconductor configuration
US6379990B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jul 6, 2019 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0136
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A membrane of the micromechanical semiconductor configuration is formed within a cavity. The membrane is formed by a crystalline layer within the substrate or within an epitaxial sequence of layers of the semiconductor configuration arranged on a substrate. The membrane is laid at the edge region on a support and is covered over by a covering layer supported on a counter-support. The support and the counter-support have a different etch rate from the membrane. Wet-chemical etching of the layer sequence with an etchant that is selective to the material of the membrane thus leads to the formation of a cavity around the membrane. Preferably, the layers are formed of differently doped materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.