Method for forming a FET having L-shaped insulating spacers

US6380039B2 · kind B2 · utility

Assignee

• INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW · BE

Inventors

• Goncal Badenes · Sabadell, ES
• Ludo Deferm · Beverlo, BE
• Stephan Beckx · Leuven, BE
• Serge Vanhaelemeersch · Leuven, BE

Key dates

• Filing date: Apr 1, 1999
• Grant date: Apr 30, 2002
• Expiry date: Apr 1, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227

Abstract

A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.