Method of fabricating semiconductor package having metal peg leads and connected by trace lines
US6380062B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2001 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Mar 9, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming ball grid array package. The ball grid array package has internal trace lines and exposed metal pegs. A metal substrate is provided. Electroplated layers are formed over metal peg regions and a die pad region on the surface of the metal substrate. A layer of substrate material at the top surface of the metal substrate is removed so that thickness of the metal substrate is reduced. Hence, trace lines, die pad and internal metal pegs are formed. A die is attached to the die pad and electrical connections from the die to the internal metal pegs are made. A molding process is carried out to enclose the die, the die pad and the internal metal pegs on one side of the metal substrate with plastic material. The lower surface of the metal substrate is etched to form external metal pegs while exposing the mold material and the bottom surface of the die pad. The internal metal pegs and the external metal pegs are interconnected via the trace lines. A soldering mask layer is formed over the package surface covering the trace lines but exposing the electroplated at the end face of each external metal peg.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.