Process for semiconductor device fabrication having copper interconnects
US6380083B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | May 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. A barrier layer to prevent copper diffusion is then deposited over the entire surface of the substrate. A dual copper layer is formed on the barrier layer. The dual layer has a copper layer deposited by PVD and a copper layer deposited by electroplating. The copper layers are adjacent to each other. The ratio of the thickness (X) of the electroplated, layer to the thickness of the PVD layer (Y) is about 1:0.5 to about 1:2. The thickness of the electroplated layer is at least about 3 &mgr;m. The thickness of the PVD copper layer is at least about 100 nm. The thickness of the two layers is selected to effect recrystallization of the electroplated copper from a small grain size (0.1 &mgr;m to 0.2 &mgr;m) to a large grain size (1 &mgr;m or greater).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.