Porous region removing method and semiconductor substrate manufacturing method
US6380099B2 · kind B2 · utility
13Cited by
5References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A given planarity of the underlying layer is ensured after removal of a porous layer. In the first step, a porous layer is filled with a preprocess solution (e.g., water). In the second step, the preprocess solution filling the porous layer is replaced with an etchant (e.g., fluoric acid), and the porous layer is etched by the etchant. With this process, the time in which the porous layer is filled with the etchant is shortened to suppress variations in progress of etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.