Automated well-tie and substrate contact insertion methodology
US6380593B1 · kind B1 · utility
7Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Dec 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.