Method and circuitry for an undisturbed scannable state element
US6380724B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Nov 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and circuitry for an undisturbed scannable state element. A scannable state element, implemented in a scan chain for testing an integrated circuit, includes both a dual-ported flop circuit and a shadow flop circuit. The dual-ported flop circuit includes both a master cell and a slave cell, while the shadow flop includes only a master cell, and utilizes the slave cell of the dual-ported flop. During scan shifting, scan data is shifted through the shadow flop and the slave cell of the dual-ported flop, bypassing the master cell. Since the data output of the dual-ported flop originates in the master cell, the state of the data in the dual-ported flop is not disturbed by the scan. Scan data may also be latched into the master cell from the scan chain or from the master cell into the scan chain through a scan data output in the slave cell. A shadow control logic circuit routes scan clock signals to either the dual-ported flop or the shadow flop, depending on whether scan shifting operations are taking place. Each shadow control logic circuit may be coupled to a plurality of shadow flops and dual-ported flops, thereby controlling a plurality of scannable state elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.