DRAM capable of selectively performing self-refresh operation for memory bank
US6381188B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) including a plurality of memory banks is capable of selectively performing a self-refresh operation with respect to only a subset of the banks. The DRAM includes a plurality of row decoders for selecting word lines of the memory cells of the memory banks, an address generator for generating internal addresses which sequentially vary during a self-refresh mode, a refresh bank designating circuit for generating refresh bank designating signals for designating a memory bank to be refreshed, and a bank selection decoder for designating one or more memory banks to be refreshed by the refresh bank designating signals and supplying refresh addresses to the row decoders corresponding to the designated memory banks according to the information of the internal addresses. The self-refresh operation is performed for only selected memory banks, or alternatively, only in those memory banks in which data is stored, thereby minimizing power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.