System and method of expediting bit scan instructions
US6381622B1 · kind B1 · utility
10Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1996 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Aug 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of expediting bit scan instructions in a microprocessor is disclosed which employs an execution unit having zero detectors organized along predetermined boundaries for detecting in parallel, the number of leading or trailing zeros in a source operand and for writing a destination index to indicate the first non-zero bit position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.