Mechanism for implementing bus locking with a mixed architecture
US6381663B1 · kind B1 · utility
6Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.