Pipelined asynchronous processing
US6381692B1 · kind B1 · utility
66Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1998 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jul 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.