Andrew Lines
26Patents
14h-index
22Co-inventors
81Inventor score
Filing activity: Jul 16, 1998 → Dec 23, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6038656A | Pipelined completion for asynchronous communication | Physics | 92 | Expired |
| US6381692B1 | Pipelined asynchronous processing | Physics | 66 | Expired |
| US7239669B2 | Asynchronous system-on-a-chip interconnect | Electricity | 47 | Expired |
| US7050324B2 | Asynchronous static random access memory | Physics | 26 | Expired |
| US6658550B2 | Pipelined asynchronous processing | Physics | 25 | Expired |
| US7161828B2 | Asynchronous static random access memory | Physics | 24 | Expired |
| US7584449B2 | Logic synthesis of multi-level domino asynchronous pipelines | Physics | 24 | Active |
| US8086975B2 | Power aware asynchronous circuits | Physics | 23 | Active |
| US6502180B1 | Asynchronous circuits with pipelined completion process | Physics | 19 | Expired |
| US8051396B2 | Logic synthesis of multi-level domino asynchronous pipelines | Physics | 19 | Active |
| US6785875B2 | Methods and apparatus for facilitating physical synthesis of an integrated circuit design | Physics | 18 | Expired |
| US6961863B2 | Techniques for facilitating conversion between asynchronous and synchronous domains | Physics | 15 | Expired |
| US8370557B2 | Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory | Physics | 14 | Active |
| US6950959B2 | Techniques for facilitating conversion between asynchronous and synchronous domains | Physics | 14 | Expired |
| US7934031B2 | Reshuffled communications processes in pipelined asynchronous circuits | Physics | 8 | Expired |
| US7814280B2 | Shared-memory switch fabric architecture | Electricity | 8 | Expired |
| US8448105B2 | Clustering and fanout optimizations of asynchronous circuits | Physics | 5 | Active |
| US7283557B2 | Asynchronous crossbar with deterministic or arbitrated control | Electricity | 4 | Expired |
| US7274710B2 | Asynchronous crossbar with deterministic or arbitrated control | Electricity | 4 | Expired |
| US8954661B2 | Binary search pipeline | Physics | 3 | Active |
| US8495543B2 | Multi-level domino, bundled data, and mixed templates | Physics | 1 | Active |
| US11037054B2 | Trace-based neuromorphic architecture for advanced learning | Physics | 1 | Active |
| US7274709B2 | Asynchronous crossbar with deterministic or arbitrated control | Electricity | 0 | Expired |
| US7698535B2 | Asynchronous multiple-order issue system architecture | Physics | 0 | Expired |
| US11908542B2 | Energy efficient memory array with optimized burst read and write data access | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.