Method for determining etch depth
US6383826B1 · kind B1 · utility
3Cited by
2References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Oct 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for determining the etch depth of a gate recess (26) in an InP based FET device (10). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.