Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film
US6384440B1 · kind B1 · utility
4Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Nov 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory is composed of a wiring layer, a bottom electrode coupled to the wiring layer, a ferroelectric film formed on the bottom electrode, a top electrode formed on the ferroelectric film, and a metal silicide layer coupled to the top electrode and located above the ferroelectric film. The wiring layer includes substantially no silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.