Single step electroplating process for interconnect via fill and metal line patterning
US6384481B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1999 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Oct 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.